Early personal computer processors supported a very limited number of peripheral devices. Each peripheral device typically requested service from a computer processor by issuing interrupt requests to the computer processor. Interrupt requests are generally controlled by an interrupt controller (IC), which prioritizes the interrupt requests among the peripherals and application programs. Manufacturers regularly developed more advanced and more diverse peripheral devices and application programs that competed for use of the processor. In addition to using the new peripherals, consumers often desired that computer manufacturers also supported legacy peripheral devices. The increasing number of peripheral devices led to increased demands to process more numerous distinct interrupt requests. Some uniprocessor systems provided support for fewer interrupt requests than the number of peripherals requesting interrupts. These circumstances led to the creation of Advanced Programmable Interrupt Controller (APIC) architectures, such as the APIC architecture specified by Intel Corporation for x86 processors. A well known Intel APIC specification supports more interrupts for uniprocessor systems than prior interrupt controllers, and also provides support for multiprocessor and multithreaded systems.
For X86 multithreaded processors, the well known Intel APIC specification supports up to 255 threads, depending on a destination mode used to manage interrupts. A physical destination mode supports up to 255 threads (i.e., 255 destinations) using an 8-bit address. Alternatively, a logical destination mode is desirable, because it enables a hierarchical cluster destination model. The well known Intel APIC specification supports 60 threads for the hierarchical cluster destination model, using a 4-bit cluster ID and a 4-bit agent mask. The Logical Destination Register (LDR) and Interrupt Command Register (ICR) hold the fields that establish these limits. Some multithreaded processors, such as x86 processors, typically implement a small number (e.g., four) threads, so the existing APIC specification is adequate. However, it is desirable to create uniprocessors that support more than 60 threads for a hierarchical cluster destination model. The existing APIC specification would require a local APIC for each thread. This requires hardware on the processor for each thread. As the number of threads increases, the amount of hardware increases and consumes valuable area on the processor. This also increases interrupt latency as current APIC systems can determine the lowest priority thread so that it can route a new interrupt request to that thread. It is desirable to support more threads, yet minimize additional processor hardware and minimize interrupt latency, while still maintaining software compatibility that may specify thread numbers.